This is directed, in general, to the manufacture of semiconductor devices.
The continuing push to produce faster semiconductor devices with lower power consumption has resulted in transistor miniaturization and higher integrated circuit packing densities with each new technology node. Moreover, transistors with smaller gate dimensions and channel width and higher packing density are conducive to faster operating devices. Along with shrinking transistor geometries, however, come a number of challenges to optimize both transistor design and integrated circuit (IC) layout design.
IC layout design involves determining the optimal placement and packing of active and passive areas over a silicon substrate, typically with the assistance of a rules based computer-aided design (CAD) programs. Active areas are defined as regions of the silicon substrate on which operative components are built, such as transistors, capacitors and resistors. Some active areas, also known as diffusion regions, are n-doped or p-doped to form transistors. To prevent conduction or crosstalk between active areas, the individual active areas are bounded by passive areas, referred to as isolation structures. Isolation structures are usually formed by filling trenches etched in the substrate with an insulator, such as silicon dioxide. In addition, other non-operative areas of the silicon substrate known as active dummy areas, which may not be doped, are distributed throughout the IC layout to help ensure that a planar surface is formed during chemical-mechanical polishing.
Numerous design rules are used to decide the dimension and relative location of active areas, passive areas and active dummy areas. For instance, transistors are designed by overlapping an active area and a polysilicon layer. The polysilicon layer can be used to form the gate electrode for one or more transistors, as well as to interconnect layers. Conventional design rules consider the minimum amount that the gate must overlap the active area (“gate overlap”), and the minimum amount that the active area must overlap the gate (“active overlap”). The rule for minimum active overlap ensures that there is an adequate area to form contacts to source/drain structures in the active area, and to maintain electrical isolation between the contacts and the gate. Still other design rules, based on transistor channel length and width dimensions, are used to predict the transistor performance characteristics, such as the on current (Ion), threshold voltage (Vth) and off drive current (Ioff). For example, the transistor expected performance may be modified to better interface with other active areas by adjusting the channel length and width, by adjusting the gate dimensions.
Conventional design rules also ensure that active dummy areas are not too close to active areas. As an example, current technology nodes may call for a minimum separation distance between active areas and passive areas of between 1000 and 2000 nanometers. In addition, there are also design rules to restrict the placement of active dummy areas near polysilicon or other gate structures, to reduce parasitic capacitance. Parasitic capacitance can be further reduced by restricting the shape of active dummy areas to be pillars instead of one large continuous block. Typically, active dummy areas have variable size, shape and location relative to active areas for different areas of the substrate.
Unfortunately, conventional design rules can produce transistors whose predicted and actual performance characteristics differ markedly. Moreover, the trend is for the disparity between predicted and actual performance to increase as the transistor dimensions are scaled down and circuit density is increased. A deviation between predicted and actual performance can cause IC malfunction. To correct these deviations, it may be necessary to redesign the IC layout. These complexities, in turn, can increase manufacturing costs and delay the production of ICs.
Accordingly, what is needed is an improved method of manufacturing transistors and integrated circuits with predictable performance characteristics and high transistor packing densities, while not suffering the deficiencies of previous approaches.